经典原版书库：计算机组成

　　《经典原版书库：计算机组成（英文版·第6版）》是一本经典的计算机组成教材，自1978年问世以来，已被多所世界知名大学选为教材。《经典原版书库：计算机组成（英文版·第6版）》知识结构合理，知识点全面完整，基本概念广泛而新颖。《经典原版书库：计算机组成（英文版·第6版）》中不仅介绍了硬件设计的原理，说明了硬件设计如何受软件需求影响，而且以流行的商用处理器作为范例，描述了各种基本知识和基本概念的应用方法和应用过程，具有很强的实用性。此外，《经典原版书库：计算机组成（英文版·第6版）》还涵盖了当今许多先进的技术和设计思想。

Contents
Chapter 1 Basic Structure of Computers
1.1 Computer Types
1.2 Functional Units
1.2.1 Input Unit
1.2.2 Memory Unit
1.2.3 Arithmetic and Logic Unit
1.2.4 Output Unit
1.2.5 Control Unit
Problems
References

Chapter 2 Instruction Set Architecture
2.1 Memory Locations and Addresses
2.1.1 Byte Addressability
2.1.2 Big-Endian and Little-Endian Assignments
2.1.3 Word Alignment
2.1.4 Accessing Numbers and Characters
2.2 Memory Operations
2.3 Instructions and Instruction Sequencing
2.3.1 Register Transfer Notation
2.3.2 Assembly-Language Notation
2.3.3 RISC and CISC Instruction Sets
2.3.4 Introduction to RISC Instruction Sets
2.3.5 Instruction Execution and Straight-Line Sequencing
2.3.6 Branching
2.3.7 Generating Memory Addresses
2.4 Addressing Modes
2.4.1 Implementation of Variables and Constants
2.4.2 Indirection and Pointers
2.4.3 Indexing and Arrays
2.5 Assembly Language
2.5.1 Assembler Directives
2.5.2 Assembly and Execution of Programs
2.5.3 Number Notation
2.6 Stacks
2.7 Subroutines
2.7.1 Subroutine Nesting and the Processor Stack
2.7.2 Parameter Passing
2.7.3 The Stack Frame
2.8 Additional Instructions
2.8.1 Logic Instructions
2.8.2 Shift and Rotate Instructions
2.8.3 Multiplication and Division
2.9 Dealing with 32-Bit Immediate Values
2.10 CISC Instruction Sets
2.10.1 Additional Addressing Modes
2.10.2 Condition Codes
2.11 RISC and CISC Styles
2.12 Example Programs
2.12.1 Vector Dot Product Program
2.12.2 String Search Program
2.13 Encoding of Machine Instructions
2.14 Concluding Remarks
Problems

Chapter 3 Basic Input/Output
3.1 Accessing I/O Devices
3.1.1 I/O Device Interface
3.1.2 Program-Controlled I/O
3.1.3 An Example of a RISC-Style I/O Program
3.1.4 An Example of a CISC-Style I/O Program
3.2 Interrupts
3.2.1 Enabling and Disabling Interrupts
3.2.2 Handling Multiple Devices
3.2.3 Controlling I/O Device Behavior
3.2.4 Processor Control Registers
3.2.5 Examples of Interrupt Programs
3.2.6 Exceptions
3.3 Concluding Remarks
Problems

Chapter 4 Software
4.1 The Assembly Process
4.1.1 Two-pass Assembler
4.2 Loading and Executing Object Programs
4.3 The Linker
4.4 Libraries
4.5 The Compiler
4.5.1 Compiler Optimizations
4.5.2 Combining Programs Written in Different Languages
4.6 The Debugger
4.7 Using a High-level Language for I/O Tasks
4.8 Interaction between Assembly Language and C Language
4.9 The Operating System
4.9.1 The Boot-strapping Process
4.9.2 Managing the Execution of Application Programs
4.9.3 Use of Interrupts in Operating Systems
4.10 Concluding Remarks
Problems
References

Chapter 5 Basic Processing Unit
5.1 Some Fundamental Concepts
5.2 Instruction Execution
5.2.1 Load Instructions
5.2.2 Arithmetic and Logic Instructions
5.2.3 Store Instructions
5.3 Hardware Components
5.3.1 Register File
5.3.2 ALU
5.3.3 Datapath
5.3.4 Instruction Fetch Section
5.4 Instruction Fetch and Execution Steps
5.4.1 Branching
5.4.2 Waiting for Memory
5.5 Control Signals
5.6 Hardwired Control
5.6.1 Datapath Control Signals
5.6.2 Dealing with Memory Delay
5.7 CISC-Style Processors
5.7.1 An Interconnect using Buses
5.7.2 Microprogrammed Control
5.8 Concluding Remarks
Problems

Chapter 6 Pipelining
6.1 Basic Concept桾he Ideal Case
6.2 Pipeline Organization
6.3 Pipelining Issues
6.4 Data Dependencies
6.4.1 Operand Forwarding
6.4.2 Handling Data Dependencies in Software
6.5 Memory Delays
6.6 Branch Delays
6.6.1 Unconditional Branches
6.6.2 Conditional Branches
6.6.3 The Branch Delay Slot
6.6.4 Branch Prediction
6.7 Resource Limitations
6.8 Performance Evaluation
6.8.1 Effects of Stalls and Penalties
6.8.2 Number of Pipeline Stages
6.9 Superscalar Operation
6.9.1 Branches and Data Dependencies
6.9.2 Out-of-Order Execution
6.9.3 Execution Completion
6.9.4 Dispatch Operation
Problems
References

Chapter 7 Input/Output Organization
7.1 Bus Structure
7.2 Bus Operation
7.2.1 Synchronous Bus
7.2.2 Asynchronous Bus
7.2.3 Electrical Considerations
7.3 Arbitration
7.4 Interface Circuits
7.4.1 Parallel Interface
7.4.2 Serial Interface
7.5 Interconnection Standards
7.5.1 Universal Serial Bus (USB)
7.5.2 FireWire
7.5.3 PCI Bus
7.5.4 SCSI Bus
7.5.5 SATA
7.5.6 SAS
7.5.7 PCI Express
7.6 Concluding Remarks
Problems
References

Chapter 8 The Memory System
8.1 Basic Concepts
8.2 Semiconductor RAM Memories
8.2.1 Internal Organization of Memory Chips
8.2.2 Static Memories
8.2.3 Dynamic RAMs
8.2.4 Synchronous DRAMs
8.2.5 Structure of Larger Memories
8.3 Read-only Memories
8.3.1 ROM
8.3.2 PROM
8.3.3 EPROM
8.3.4 EEPROM
8.3.5 Flash Memory
8.4 Direct Memory Access
8.5 Memory Hierarchy
8.6 Cache Memories
8.6.1 Mapping Functions
8.6.2 Replacement Algorithms
8.6.3 Examples of Mapping Techniques
8.7 Performance Considerations
8.7.1 Hit Rate and Miss Penalty
8.7.2 Caches on the Processor Chip
8.7.3 Other Enhancements
8.8 Virtual Memory
8.8.1 Address Translation
Problems
References

Chapter 9 Arithmetic
9.1 Addition and Subtraction of Signed Numbers
9.1.1 Addition/Subtraction Logic Unit
9.2 Design of Fast Adders
9.2.1 Carry-Lookahead Addition
9.3 Multiplication of Unsigned Numbers
9.3.1 Array Multiplier
9.3.2 Sequential Circuit Multiplier
9.4 Multiplication of Signed Numbers
9.4.1 The Booth Algorithm
9.5 Fast Multiplication
9.5.1 Bit-Pair Recoding of Multipliers
9.5.2 Carry-Save Addition of Summands
9.5.3 Summand Addition Tree using 3-2 Reducers
9.5.4 Summand Addition Tree using 4-2 Reducers
9.5.5 Summary of Fast Multiplication
9.6 Integer Division
9.7 Floating-Point Numbers and Operations
9.7.1 Arithmetic Operations on Floating-Point Numbers
9.7.2 Guard Bits and Truncation
9.7.3 Implementing Floating-Point Operations
Problems
References

Chapter 10 Parallel Processing and Performance
10.1 Hardware Multithreading
10.2 Vector (SIMD) Processing
10.2.1 Graphics Processing Units (GPUs)
10.3 Shared-Memory Multiprocessors
10.3.1 Interconnection Networks
10.4 Cache Coherence
10.4.1 Write-Through Protocol
10.4.2 Write-Back protocol
10.4.3 Snoopy Caches
10.4.4 Directory-Based Cache Coherence
10.5 Message-Passing Multicomputers
10.6 Parallel Programming for Multiprocessors
10.7 Performance Modeling
10.8 Concluding Remarks
Problems
References

Appendix ALogic Circuits
A.1 Basic Logic Functions
A.1.1 Electronic Logic Gates
A.2 Synthesis of Logic Functions
A.3 Minimization of Logic Expressions
A.3.1 Minimization using Karnaugh Maps
A.3.2 Don抰-Care Conditions
A.4 Synthesis with NAND and NOR Gates
A.5 Practical Implementation of Logic Gates
A.5.1 CMOS Circuits
A.5.2 Propagation Delay
A.5.3 Fan-In and Fan-Out Constraints
A.5.4 Tri-State Buffers
A.6 Flip-Flops
A.6.1 Gated Latches
A.6.2 Master-Slave Flip-Flop
A.6.3 Edge Triggering
A.6.4 T Flip-Flop
A.6.5 JK Flip-Flop
A.6.6 Flip-Flops with Preset and Clear
A.7 Registers and Shift Registers
A.8 Counters
A.9 Decoders
A.10 Multiplexers
A.11 Concluding Remarks
Problems
References

Appendix BThe Intel IA-32 Architecture
B.1 Memory Organization
B.2 Register Structure
B.3 Addressing Modes
B.4 Instructions
B.4.1 Machine Instruction Format
B.4.2 Assembly-Language Notation
B.4.3 Move Instruction
B.4.4 Load-Effective-Address Instruction
B.4.5 Arithmetic Instructions
B.4.6 Jump and Loop Instructions
B.4.7 Logic Instructions
B.4.8 Shift and Rotate Instructions
B.4.9 Subroutine Linkage Instructions
B.4.10 Operations on Large Numbers
B.5 Assembler Directives
B.6 Example Programs
B.6.1 Vector Dot Product Program
B.6.2 String Search Program
B.7 Interrupts and Exceptions
B.8 Input/Output Examples
B.9 Scalar Floating-Point Operations
B.9.1 Load and Store Instructions
B.9.2 Arithmetic Instructions
B.9.3 Comparison Instructions
B.9.4 Additional Instructions
B.9.5 Example Floating-Point Program
B.10 Multimedia Extension (MMX) Operations
B.11 Vector (SIMD) Floating-Point Operations
B.12 Concluding Remarks
Problems
References